3D MOSFET Transistors: The FinFET

Home Descriptive 3D MOSFET Transistors: The FinFET

Introduction

For decades, various types of the 3D transistors have been proposed by the developers. FinFET transistors have become the prevailing type of technology, considering that the process of fabricating the device structure is relatively uncomplicated and compatible with the conventional planar channel MOSFETs. The main producers of the 3d FinFETs are STMicroelectronics, Global Foundries, IBM, and Intel. Thus, it is important to observe the main features, advantages, and challenges of the FinFET technology to make the prediction concerning its future development.

History and Classification of FinFETs

The world’s first commercial model of a three-dimensional semiconductor device Matrix 3-D Memory from Taiwan Semiconductor Manufacturing Corporation (TSMC) and Matrix Semiconductor was presented at the end of 2001 (Intel, 2011). It should be noted that the attempts to create three-dimensional integrated circuits have been undertaken by universities, research laboratories, and individual scientists since the beginning of the 1970s. In addition to the use of polycrystalline silicon, the change in the structure that was supposed to be realized with the aid of a laser beam, other constructive solutions were also provided in these works, allowing several two-dimensional chips to be placed one above the other.

Intel Corporation announced the beginning of mass production of processors based on 22 nm technology of 3D FinFETs in 2011.The world’s technological level was the following: 28 nm in 2012, 14 nm in 2014, and 12 nm in 2016. As it has been mentioned above, the leading producers of the 3d FinFETs include STMicroelectronics, Global Foundries, IBM, and Intel. Symmetric and asymmetrical n- and p-channel FinFETs were designed, which characteristics were optimized for high-speed performance and low threshold voltage respectively.

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Structure of FinFET Transistor

Transistor with a double gate of the 3d structure FinFET has the following structure. In this device, a thin silicon body (fin) is wrapped with a shutter, which forms two aligned channels located on both sides of the silicon body. The protruding front region of the body is the source of the transistor, and the protruding posterior region is the drain. The current flows through the plane parallel to the plane of the body, and although the gates extend beyond this plane, the structure of the FinFET can be regarded as quasi-planar. The active width of the device is equal to the height of the body-column, and it can be increased by the parallel inclusion of many columns. In its topology, FinFET does not differ from the traditional MOSFET, except that the active region is formed by inserts and does not represent a flat rectangle. It is easy to set up the manufacturing of FinFET on the basis of the MOSFET manufacturing since all the necessary technological operations are widely used in modern semiconductor manufacturing and are well developed. The most critical parameter of this structure — the thickness of the channel, depends on the resolution of the lithography process.

The fin in the 3d FinFET transistor is located and attached to the substrate. The height of the fin Hfin is defined as the height from the surface of the oxide insulation area to the upper part of the body. TFOX is the thickness of the protective oxide for insulation of the device. The depth of drain-source p-n-junctions is represented by xj. The heat generated in the channel transmits to the substrate through the fin body, which is connected to it.

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Fabrication and Challenging Parameter in the Manufacturing Process of FinFETs

Fabrication procedures of the FinFETs are the following. First, crystalline silicon is grown and its shape is formed for cutting the material into round plates. Next phase includes the precise fitting of the plate dimensions and checking it for cleanliness, followed by cleaning and polishing it with gas and liquids and/or plasma chemical methods. Then the epitaxial deposition of a uniform layer of a substrate-like substance occurs at the atomic level, which serves as the foundation for leveling. A masking layer is used as well — it protects the deposited layer of silicon atoms from various effects during other steps.

The next step is photolithography. Under special radiation of different wavelengths, chemical markers appear on the surface of the plate that will react with subsequent active substances. By the chemical method and the diffusion method, due to the action of active substances (phosphorus, boron), p- and n- regions, micro-transitions, and grooves are formed, which will become future semiconductor elements. Then, the photolithographic processing in the oxide layer of certain areas should be carried out. It will create markers (alloyed sections) for applying metallic elements (wiring, contacts) through vacuum metallization. Excessive metal is removed, and the one that is applied correctly is thermally fixed, or soldered. Thus, the finished elements of the microchip are formed.

Applying the required number of levels of dielectric and metal with subsequent photolithography and processing is the next step. Above the uppermost layer, one may apply several layers of metal and dielectric to protect and correctly dissipate the heat. Then the last phase occurs — it includes passivation of the plate, tests, cutting the material into microchips, mounting it on the processor case, connecting the leads, and rejecting the excessive materials (LexInnova Technologies, 2015).

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The challenging parameters in the manufacturing process of Finfets include the following. Fist, for the successful manufacturing process, one should execute the process of alloying in a specific way. Local alloying of a three-dimensional FinFET transistor is required to suppress the undesirable bulk closure next to the drain-source p-n junctions at the depth of xj. Local alloying is carried out in the lower part of the drain-source region and is called a through-stopper. The manufacturers proposed a new method of forming a through-stopper with the usage of lateral alloying, the one involving ion scattering from the isolation region (SiO2) aimed to realize the technology of manufacturing of FinFETs. According to this technology, the ions for the through-stopper are implanted into the insulation region at an angle of 0 °. Implanted ions are common in the isolation region, and some of the ions, as a result of localized alloying, are scattered and laterally penetrate into the fin. Previously implanted in the isolation region ions are formed on both sides of the vertical fin and at the upper rigid mask (Si3N4).

The alloying concentration of the impurity in the fin is a key parameter that influences the design of the sub-threshold slope, the reduction of the drain-induced barrier, and the mobility of the carriers. From the point of view of carrier mobility, the level of doping of the body should be as low as possible. However, a lowering of the level of body alloying is the reason for an increase of the drain-induced barrier and sub-threshold slope.

Advantages of the FinFET Technology

The production of the 3d FitFET transistors has two obvious advantages. The first is a significant reduction in prices for a fixed device. The second is an increase in the number of transistors on a chip with a speed no less than Moore’s law allows, considering the number of devices per area unit. Intel produced the 22 nm FitFET transistors that reduce the voltage of 0.7 V by 37%. Their active power in continuous mode is by 50% lower in comparison to the 32-nm logic. The company achieved a 19% improvement in the Ivy Bridge processor’s power consumption (77 watts at a clock frequency of 3-3.5 GHz in comparison to 95 watts for 32-nm Sandy Bridge processors).

The Problems of Power Consumption of FinFETs

Power consumption problems of FinFETs are directly related to the leakage current Ioff. When the transistor is closed, its resistance is huge, and the active power during that period is P = Ioff2 R. Thus, it is quite important to lower the leakage current in order to decrease the power consumption.

Controlling the width of the fin (Wfin) is very important at a given angle since the width significantly affects the short-channel effect. As one may observe, with a decrease of the fin width from 12 to 8 nm, open transistor current ION decreases by 18%, while 100 times decrease of the leakage current IOFF occurs, leading to the active power decrease by 1002 times. Thus, the leakage current IOFF and the active power of the transistor are very sensitive to the width of the “fin”, which the producers should control to maintain a limited distribution of the leakage current IOFF.

One may consider the effect of the distance between the p-n junction of the drain and the source at a fixed channel length of 14 nm. It is possible to observe the ratio between the open transistor current ION, the leakage current IOFF, and the distance between the p-n junctions. Here, the alloying of the body is Nb = 1 ? 1017 cm-3. One may see that the open transistor current ION and the leakage current IOFF significantly decrease with the increasing distance. Particularly noticeable (up to 100 times) changes of the leakage current IOFF correspond to the 1002 increase of the active power when the distance changes from 10 to 24 nm. If the fin’s length is greater than 14 nm, it is possible to say that the source and drain are negatively overlapping. There are the characteristics of SS and DIBL as the functions of distance. With increase of the distance between p-n-junctions, the characteristics of SS and DIBL improve significantly. However, one can observe the lowering of both the open transistor current ION and the leakage current IOFF during the distance increase. If DIBL is stored at 100 mV / V, the distance should be greater than 18 nm when the body is alloyed to 1 ? 1017 cm-3. With a moderate alloying of the body at 2-3 ? 1017 cm-3, the distance can be reduced to 14 nm.

Therefore, further reduction of the overall dimensions of the 3d FinFET transistors will allow to equip the devices with a large number of transistors, thereby increasing the performance, but it will not significantly improve energy consumption. Thus, there is a certain overall limit that determines the feasibility of using these transistors.

Future of Finfet and Other MOSFET Transistors

Due to energy consumption problems that do not allow the reduction of the size of the FinFET transistors, this technology is currently not particularly relevant for such major microelectronics manufacturers as IBM and STMicroelectronics. For this reason, it will be replaced by other technologies. For example, the experts from IBM have already prepared a new type of technology that will reduce the transistor size to 5 nanometers. Donating a promising FinFET architecture in favor of the new technology, the company’s specialists developed a stack structure that consists of four superimposed nano-sheets. According to the calculations, the new structure of transistors will allow to pack 30 billion of them on a chip which size is similar to that of the small coin. Apart from this, the new structure promises a high increase in chip performance and efficiency.

This technology is a further upgrade of the 7-nm technology developed by IBM in 2015, in a tandem with the companies GlobalFoundries and Samsung (Nelson, 2017). The experimental samples of such chips are numbered around 20 billion transistors per a chip, and it was achieved through the introduction of new materials and production technologies. The manufacturers expect that the chips built on the basis of 7-nm technology will appear on the market in about 2019 (Nelson, 2017).

As mentioned above, 5-nm chips are manufactured by stacking several layers of silicon nano-sheets. It allows the control signal to be sent directly to four separate transistor gates, while the FinFET transistors have three independent gates and three channels. 5-nm transistors are manufactured with the usage of the extreme ultraviolet lithography (EUVL) technology that allows “drawing” the images on a substrate better by using shorter-wave and high-energy radiation, unlike it is done through other methods. This, in turn, means that with this method, the producers will be able to create smaller chip elements with higher quality. At the same time, the new EUVL technology allows the continuous adaptation adjustment right during the production process.

Compared to 10-nm chips, 5-nm chips will have 40 times more performance, and the amount of energy consumed by them will be reduced by 75% during the processor’s performance of the specially optimized tasks. According to the available forecasts, the first commercial 5-nm chips can appear on the market not earlier than in 4-5 years.

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Conclusion

STMicroelectronics, Global Foundries, IBM, and Intel are the major producers of the 3d FinFETs. Intel Corporation announced the beginning of mass production of processors based on 22 nm technology of 3D FinFETs in 2011.The world technological level is the following 28 nm in 2012; 14 nm in 2014, and 12 nm in 2016.

The structure of the FinFET transistor includes a thin silicon body (fin), which is wrapped with a shutter, which forms two aligned channels located on both sides of the silicon body. The protruding front region of the body is the source of the transistor, and the protruding posterior region is the drain.

The manufacturing process of the FitFET transistors is the complicated set of procedures that include cleaning and polishing with gas and liquids and/or plasma chemical methods, photolithography, passivation of the plate, tests, cutting into microchips, mounting on the processor case and connection of the leads, and rejection. Fabrication procedures of the FinFETs include the new advanced method of forming a through-stopper with the usage of lateral alloying through ion scattering from the isolation region (SiO2).

The production of the 3d FitFET transistors has two obvious advantages: a significant reduction in prices for a fixed device and an increase in the number of transistors on a chip with a speed not less than Moore’s law allows considering the count for the number of devices per area unit. However, it has some negative issues. For instance, the power consumption problems of FinFETs are directly related to the le are directly related to leakage current Ioff, which depends on the width of the fin and the distance between the p-n junction of the drain and the source. Due to the energy consumption problems that do not allow the reduction of the size of the FinFET transistors, this technology is currently not particularly relevant for such major microelectronics manufacturers as IBM and STMicroelectronics. It will be replaced by other technologies — for example, the IBM technology, which assumes the stack structure of the transistor consisting of four superimposed nano-sheets.

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